Since the invention of non-volatile memory cells having both electrically erasable and electrically programmable capabilities as disclosed in U.S. Pat. No. 4,115,914 issued to Harari on Sept. 26, 1978; U.S. Pat. No. 4,203,158 issued to Frohman-Bentchkowsky et al on May 13, 1980, the high volume commercial production of EEPROMs that employ the thin tunnel dielectrics for electrically erasing and electrically programming has gradually become a reality. These EEPROMs consist of one selection device in series with a memory device that has a floating gate over the channel and the tunnel dielectric area on the drain, and a stacked control gate over the floating gate. The programming of the memory device is achieved by applying a suitable potential across the drain and the control gate of the memory device to cause charge carriers to tunnel through the tunnel dielectric from the floating gate to the drain. The erasing of the memory device is achieved by applying a suitable potential across the control gate and the drain of the memory device to cause charge carriers to tunnel through the tunnel dielectric from the drain to the floating gate. In order to minimize the memory cell size, a flash EEPROM memory cell was introduced. The flash EEPROM cell is the hybrid of EPROM and EEPROM memory cell. The most common type of flash EEPROM is similar to EPROM in structure except the gate oxide underneath the floating gate is in the range of 70 A to 200 A. The programming of the flash EEPROM is achieved by applying a suitable potential at the drain and the control gate and grounding the source as in the EPROM to inject channel hot charge carriers into the floating gate. The erasing of the flash EEPROM is achieved by applying a suitable potential at the source and grounding the control gate to tunnel charge carriers from the floating gate to the source through the thin gate oxide. The key drawback of this flash EEPROM is the large thin gate oxide area under the whole floating gate. The yield and the reliability of the flash EEPROM are limited by the defect density of the large thin gate oxide area. Another drawback of this flash EEPROM is the low gate controlled junction breakdown at the source junction due to the thin gate oxide over the source junction.